A broad definition of “Digital Twin or Virtual Model” is a technology of creating a virtual replica of the physical object, system, or process. A digital twin is not just a static 3D model but a dynamic one that simulates the behavior and performance of the physical system in real-time. The high-level idea is that the same inputs given to the physical system can be given to the Digital Twin model in real time and then run the simulation. Thus, having a chance to understand the process/hardware, analyze the performance, and get a gist of potential improvements to be applied back to the physical asset.

The potential of Digital Twin is phenomenal. As the concept and technology evolve, the collaborative and predictive impact of digital twins cannot be undermined. We talked to our Lead Engineer, Rajat Shetty, having 5+ years of experience working in Digital Twin, to understand the concept and the scope of this technology better. Read on to know his experience of working in the field and what you can expect if you are planning to have a career in this domain. 

Q1. Can you explain what Vayavya Labs does in the domain of Digital Twin?

Ans: Vayavya Labs is actively involved in creating the virtual models of various embedded physical boards, complex semiconductor SoCs (Systems on Chips), and ECUs (Electronic Control Units) in vehicles that use these SoCs. The process usually starts with identifying the various individual components required for modeling, creating the individual models of these IPs, and stress testing them at the unit level, then integrating the models so that the combined integrated model virtually represents the original physical device.

Q2. Why do you need a Virtual Model? 

Ans: I will try and explain using a few examples.

• A virtual model can be used as a replacement for physical devices when it comes to software development and testing. This requirement comes due to scarcity of the physical device, either due to the time that goes into manufacturing/synthesizing the hardware or the limited quantity of hardware setup present in the organization itself. Digital twin provides a perfect alternative to continue the work instead of prolonged wait cycles.
• Shift Left Strategy: The process involved in creating a virtual model of the device is much simpler compared to designing and manufacturing physical SoC. Therefore, the time taken to create a virtual model, and make it available is less as compared to the actual SoC chips being ready and available. This enables the software developers to start with the design, development, and testing of the driver, and application much earlier and have a good amount of work even before the hardware is ready. It saves considerable time before the product roll-out and gives a sheer advantage of being ahead of the market needs.
• Architectural/Design exploration and early fault detection: With virtual modeling, designers can create and simulate various design alternatives, and compare their performance and characteristics to identify the most optimal one. This approach allows for rapid iteration and modification of design ideas without the need for physical prototypes, which can save time and costs and thereby explore the different design options and identify the best solution. Virtual modeling can be used to simulate the performance and behavior of a system under different operating conditions and scenarios, which can help detect faults and potential failure modes early in the design process. By identifying and addressing these issues early, designers can improve the reliability and safety of the product, reduce development costs, and accelerate time-to-market.

Q3. What is the future of Digital Twin technology?

Ans: According to the stats, “The global digital twin market is estimated to be from USD 6.9 billion in 2022 to USD 73.5 billion by 2027, at a CAGR of 60.6% during the forecast period.”

As modern vehicles are becoming increasingly software-driven, the lines of code in a vehicle are exponentially increasing. On the other hand, the time to roll out a new vehicle is decreasing. OEMs are actively relying on Virtual ECUs to start their software architecture definition as well as software development early enough. They are increasingly relying on a digital twin of the SoC platform to do the validation of this complex software.

Q4. How is Virtual Modeling different from Device drivers or Firmware development?

Ans: As a device driver developer you would be concerned about programming the device correctly. This involves the implementation of the device driver APIs typically for initializing, configuring the device, and performing the transfer or receive operations. Some drivers often involve complex descriptor programming as well. However, you rarely bother about the internal working of the different hardware blocks and the reaction in the hardware that your inputs trigger. And there is a fair assumption that the hardware works to your inputs.

Whereas, as a Virtual model developer, you would be defining the hardware structure, the different internal blocks involved, implementing relevant functionality of these internal blocks, and the interconnect between them. A lot of the virtual model implementation also involves implementing a state machine that reacts to the different inputs to the model from the driver software.  

Q5. As an individual with the device driver and embedded system knowledge, how would you use your existing skill sets in virtual modeling?

Ans:  Virtual modeling is all about knowing the working of the hardware. The experience of reading the datasheet would help understand the hardware device, and its outer structure, identifying the different blocks involved, and the functionality associated with each block.

The experience of C programming/device driver would help model the register, program the reactions to various register inputs, program the functionality of different blocks, and consequently the combined functionality of the model.

Also, the device driver knowledge would be helpful in the unit, system-level testing to validate the model’s functionality.

Q6. What is the training curriculum at Vayavya Labs to get you started with Virtual Modeling?

Ans: The training process at Vayavya involves the following steps:

• Comprehensive training in C++ starting with basics, OOPs-based concepts followed by topics like templates, and leveraging of data structures provided by the standard library.
• In-house framed assignments to apply and test the C++ concepts, to help you develop insights and grasp the core concepts.
• Studying the C++ libraries used specifically for virtual modeling and corresponding assignments to apply the learnings.

Q7. What are the skills required to start a career in Virtual Modeling?

Ans: The starting point is a basic understanding of computer architecture and embedded systems. If you have experience in developing device drivers then that along with knowledge of different interface or communication protocols like I2C, CAN, SPI, Ethernet, etc is of great help. Yes, you need to know C++ and the modeling libraries, and some core concepts involved in modeling. However, C++ and core modeling concepts can be learned if you are a sound embedded systems developer. 

Above all, the passion to learn something new, cutting edge and succeed is the most important skill!

Q8. What is the interview process for the position of Digital Twin Engineer at Vayavya Labs?

Ans: The interview process at Vayavya involves two technical rounds- R1 and R2 followed by an HR interview R1 and R2 are both technical rounds that deal with questions about C programming, Computer architecture, and Embedded Systems basic knowledge. You are expected to be a good programmer and problem solver. As an interview tip, I would suggest that it is good to have a fair knowledge of C++ before appearing for the interview.

Q9. What do you love about this work? What would be your advice to engineers who are looking to make a transition from embedded software development to Virtual Model development? What kind of opportunities and career paths can they expect?

Ans: I love the dynamic nature involved in the work. With each new model, comes new complexity, new design approach, and new learnings. The excitement to work on every new module always keeps me on the edge of my seat. It excited me to be at the forefront of innovation and contribute to the development of new technology.  I especially want to mention Vayavya Labs here and thank them for providing diverse opportunities and support in both technical and non-technical aspects to excel in my career.

For people looking to make the transition, the only advice would be to get the basics strong and correct as this domain involves understanding the hardware to the core depth. Have good programming knowledge as it involves a vigorous amount of coding to come up with the virtual twin of the block and write the drivers to test the model.

Outcomes/Opportunities/Learnings:

Working in Digital Twin, an individual can expect to get a core insight into the various individual IP blocks, and the integration complexity involved to get all the blocks combined to make it work as a virtual twin of an SoC. Get a good knowledge about the various modeling platforms where the models are developed, that are used by various semiconductor giants. Virtual modeling allows engineers to explore new ideas and technologies before they are implemented in the real world.

Besides Virtual modeling Engineer, In terms of career opportunities and paths, virtual modeling in SoC/embedded devices offers a range of options. Some potential career paths include:

1. Embedded software engineer: Working in the Virtual Modeling stream, doesn’t mean that you are taking a completely different path than being an Embedded software engineer, rather I would say it’s an additional feather on the hat.
2. Design engineer: SOC Design Engineer, will be responsible for designing and developing complex SOC systems that are used in various applications.
3. Verification engineer: Verification Engineers are responsible for verifying the functionality of the SOC system design. They work with the design team to create test plans and use virtual modeling tools to simulate and validate the design.
4. Physical Design engineer: Physical Design Engineers are responsible for translating the SOC system design into a physical layout and involve in designing and developing hardware for SoC/embedded devices.

If this motivates you to work in the Digital Twin domain and know more about it, reach out to us with your resume at career@vayavyalabs.com. We would be happy to talk to you.