Imagine a datacenter powering critical cloud services, silently compromised by a tampered chip inserted during manufacturing. In most cases, the malware would be practically impossible to remove and could persist across formats/reinstalls !
This has happened in the past, some of the notable ones being:
This is where Roots of Trust (RoTs) come in – these are tamper-resistant components embedded in hardware that ensure systems boot securely and prove their integrity from the silicon up.
While proprietary RoTs have long dominated, open-source RoTs are gaining momentum for their transparency and collaborative potential. Developed by communities and industry consortia, these solutions offer auditable, cost-effective security for datacenters, IoT, and edge devices, aligning with standards like NIST SP800-193.
This two-part blog dives into open-source RoTs: Part 1 explores the “why” (their critical role) and “what” (core concepts and benefits), while Part 2 will cover architecture, integration, and how one can add this to their next system.
A Root of Trust (RoT) is a tamper-resistant hardware component to establish a secure foundation for a system. The RoT is designed to perform critical security functions, such as generating and storing cryptographic keys, attestation of device identity, including verifying the integrity of firmware and software, and securely booting the system.
RoTs perform three essential functions:
In modern threat scenarios, supply chain attacks can embed malware in chips before they reach users, as seen in real-world incidents; these can persist across reboots and can be virtually undetectable by software running on the system.
RoTs counter these by:
RoTs are indispensable in datacenters, IoT, and edge computing, where confidential computing protects sensitive workloads and compliance with standards like GDPR or NIST SP800-193 is non-negotiable. Without RoTs, a single compromise could lead to data leaks or system-wide failures.
Proprietary RoTs
Proprietary solutions offer robust security and are often certified against standards like FIPS 140-2.
Their drawbacks are vendor lock-in and potential undiscovered vulnerabilities due to a lack of transparency.
Some of the well-known proprietary implementations are Intel Software Guard Extensions(SGX), Google’s Titan Security Chip, ARM TrustZone, Microsoft Pluton Security processor, TPM(Trusted Platform Module) implementations by semiconductor vendors (STMicro, Infineon, Broadcom), HPE Silicon Root of Trust, and Qualcomm Secure Processing Unit (SPU).
While fewer in number compared to proprietary options, projects like Caliptra and OpenTitan are gaining traction, particularly in data centers and edge computing.
Open-source RoTs address key drawbacks of proprietary solutions, including vendor lock-in and a lack of transparency. By making their designs public, they invite community scrutiny, reducing the risk of backdoors and fostering collaborative improvements. They also lower costs through reusable designs and support emerging needs.
Open-source RoTs are developed by collaborative ecosystems, often backed by industry leaders, academics, and startups. Hosted on platforms like GitHub, these projects provide fully auditable Register-Transfer Level (RTL) code, firmware (often in secure languages like Rust), and verification tools.
Open source RoTs typically include everything one needs to implement a RoT:
The open-source model delivers unique advantages. Transparency allows anyone to inspect for vulnerabilities, fostering trust. Community contributions accelerate innovation, as seen in projects under groups like the CHIPS Alliance or Open Compute Project (OCP).
Cost savings come from reusable IP blocks, which can be integrated into SoCs without expensive licensing.
Two such open-source RoT implementations are Caliptra and OpenTitan
Caliptra stands out as a collaborative effort to standardize hardware security. Announced in 2022 by the CHIPS Alliance, it originated from OCP and has since open-sourced its RTL code, firmware, and verification tools on GitHub. The firmware is mainly written in Rust for safety.
Caliptra integrates as an IP block within an SoC, booting early to measure and attest the system’s state. It features a RISC-V microcontroller, 128KB SRAM (though specs can vary), and crypto accelerators for SHA, ECC, AES, and more.
It operates in active or passive profiles, using mailbox interfaces for communication with the host SoC.
Launched in 2018, it’s the first silicon RoT to open-source its entire design, from RTL to verification tools, under the Apache 2.0 license. Hosted on GitHub, it invites contributions via a community-driven model, with regular updates and transparent roadmaps. Recent milestones, like the 2025 release of the Earl Grey chip, demonstrate its real-world viability.
OpenTitan uses a RISC-V Ibex core, paired with cryptographic accelerators (AES, HMAC, RSA, ECC) and secure storage for keys and fuses.
It supports secure boot, measured boot, and attestation, making it versatile for datacenters, IoT, and embedded systems.
Existing cryptographic foundations like RSA and ECC—used for secure boot, attestation, and key exchange in Roots of Trust (RoTs)—will be breakable by quantum algorithms in hours! To remain trustworthy, RoTs must adopt post-quantum cryptography (PQC), such as lattice-based (CRYSTALS-Kyber) or hash-based (SPHINCS+) schemes as currently standardized by NIST.
Open-source implementations like Caliptra and OpenTitan provide an adaptable framework where PQC can be integrated into the secure boot chain and attestation flows. Their transparency and update mechanisms ensure that as PQC standards evolve, the RoT remains relevant for devices over decades, even against quantum-capable adversaries.
Open-source Roots of Trust are revolutionizing hardware security by making it transparent, collaborative, and accessible. This enables us to build secure systems without proprietary barriers, paving the way for a standardized, trustworthy firmware running on everyday systems.
In Part 2, we’ll explain the architecture of these solutions, from RTL integration to firmware flows, and guide implementation. Stay tuned!