Introduction:

Efficient usage of power by the System on Chip (SoC) for running a given application is one of the key for a product to be successful. Consumption of power by the SoC can be broadly classified into two categories, first category being the process technologies used (that includes the transistor technology used such as MOSFET, FinFET etc., and the process node used (10um to latest 5nm)). Second category being the Software that runs on the SoC will switch on and off the sections of the SoC on need bases, this directly helps in efficient power usage by the SoC. In this document we will be focusing on the second category.

Power Domains in a SoC:

We can broadly classify the different power domains in a SoC as shown in the below diagram.

Different components in the Power domains:

Core – This includes all the CPU cores, program memory, data memory, bus architectures (AHB/AHB lite etc.,)

PLL – Phase locked loop which generates clocks to all the domains. The clock generation are normally configurable from Software.

ADC – Analog to digital converter, also configurable from Software.

ANALOG – Analog front end, used in RF data acquisition and transmission from the Tuner, also configurable from Software.

IO – All the IO peripherals which sends and receives data. IO range basically from GPIO, I2C, SPI to complex IO as SD, USB, Ethernet etc.,

Tuner – Tuner to tune to a particular band of RF, also configurable from Software.

Thumb Rule of Power optimisations:

1. As mentioned earlier the software that runs on the SoC can switch on and off these power domains on need basis, resulting in no power consumption by that module.

2. Also the Software can reduce the operating frequency to reference clock of these domains when there is no data to be processed by these modules and when there is availability of data then the Software will raise the operating frequency to required level (normal clock) so that data can be processed faster.

Challenges in implementing Power Optimisation:

In a single CPU model the Software that runs on the SoC can very easily determine which domains needs to be switched on and off and which domains needs to be put to work with reference clock or normal clock and vice versa.

The challenge comes in a multi CPU model where the decision making of switching to on/off or moving the operating frequency from reference clock to normal clock and vice versa by the Software running on one CPU can affect the normal operation of another module and also we need to consider a lot of time rates at which the data can come and how much of time is required to process. Following are few of the cases,

Shared Memory:

A shared memory is used by all the Software running on all the CPU’s and initially the operating frequency is set to normal clock. When one CPUs is not accessing this shared memory then the Software running on that CPU cannot bring down the operating frequency to the reference clock because other CPU’s can be using it. So to achieve power optimization, a collective decision between all the CPU’s has to be there. To implement a collective decision there are multiple schemes and one of them is to make one CPU’s as the decision maker and all other CPU’s have to tell if a module has to be switched on/off or change operating frequency to normal to reference or vice versa. Based on the inputs the decision is made.

CPU Core:

When a CPU is waiting for the data to come from another CPU or a RF front end then this CPU can be put in reference clock and when data is available then it can be put back to normal mode. The decision make CPU will put other CPUs in normal or reference mode based on the availability of the data. Also when decision maker CPU is idle then this CPU can itself go to work in reference mode and when data is available then it can go to work in normal mode. The switching to reference has to be very fast so that there is no data loss.

IO:

When there is no data to be sent from the IO, then the IO can be disabled and the input clock source can be cut off completely. When there is data to be received and based on the IO being synchronous or not, the IO can be disabled and the input source can be cut off completely.

For a given application all the IO present in the SoC may not be used, so based on the application needs Software can switch off the IO and the input clock source completely.

ADC:

When there is no data coming from the tuner then the ADC can be switched back to reference clock and when data is available the ADC can be switched back to normal clock. Also all the CPUs can be kept in reset state when ADC is switched to reference clock and release all CPUs when ADC is switched to normal clock.

Testing Power Optimisation:

The thermal dissipation has to be measured for all the power domains when running at normal mode and reference mode for minimum and maximum data input rate.

Standards Requirement:

Based on which domain the SoC will be used, the minimum and maximum power levels defined by that domain has to be achieved. For example, a SoC to go in to a mobile platform it has to achieve the necessary SAR values.

This blog discusses and outlines some of the different software schemes used to achieve the power optimisation and is based on the personal work experience of the author.