The cost of IC production at leading process nodes is rising exponentially due to increased complexity of fabrication process. The cost at 28nm is twice as much that of current nodes (45nm) therefore the stakes are high for a SoC company in releasing a faulty or under-performing IC. Hence verification process in IC development plays an important role and is of utmost importance. At present levels of IP integration, verification budget and time contribute significantly to a project cost and time, and they are projected to increase rapidly at leading process nodes.

As much of the system functionality in a SoC is under the control of an embedded CPU core/cores, verification scenarios require development of test-software. At present, verification engineers translate such scenarios into test-software manually, placing a limit on the number of scenarios that can be developed. Combining test-software with the intent of generating new scenarios becomes effort intensive and error prone thereby limiting scenario exploration. This insufficient approach leads to under-verification with many system-level issues/bugs unexplored.


SOCX-Verifier from Vayavya Labs addresses functional verification challenges at SoC level through automatic test-software generation from user-specified scenarios. SOCX-Verifier provides a rich and intuitive scenario specification mechanism for verification engineers to express scenarios from simple to complex and the means to combine scenarios using temporal and hierarchical relationships. Users can specify constraints on scenario level or across sets of scenarios for SOCX-Verifier to explore different use-cases for comprehensive system-level verification.

SOCX-Verifier also provides a staged methodology for verification by enabling users to progressively cover scenarios spanning from basic (HW/SW interaction) to application-level to performance-centric.

Retaining verification intent as scenario specification provides added benefit of reusing the specification across different design projects and test-platforms and also doubles up as an added documentation.

SOCX-Verifier drastically reduces the effort and time spent in scenario conversion and empowers engineers to think more in terms of scenarios. At present levels of SoC integration which comprises of 40-50 IPs and future fabrication processes’ promising more, system-level functional verification through SOCX-Verifier’s automated test-software development provides a scalable and an effective solution to deliver on quality of verification and TTM.

SOCX-Verifier comes packaged with SOCX-Abstractor which provides the abstraction over underneath DUT (SoC) and TB for seamless scenario specification and execution across different verification testplatforms like simulation, emulation or virtual-prototype. SOCX-Abstractor comprises of SOCX-OS, a verification-aware lightweight and configurable operating system to enable multi-threaded testapplication.


The quality of system-level verification is dependent on low-level driver layer which expose the underneath IP/device to test-application level. SOCX-Abstractor provides a unique and advanced feature of automatic driver-generation capability when model is specified in DPS format (refer) or accept legacy driver-models. Driver-model generated through DPS format provides much better abstraction of underneath IP thereby enabling higher coverage and extensive use-cases.

With rising cost of IC fabrication at leading process nodes, forthcoming SoC’s market success will be defined by the quality of verification and the cost and time taken to achieve it. SOCX-Verifier delivers on current challenges in SoC verification to assist in comprehensive verification in a cost-effective and scalable way.


The SOCX-Verifier flow at a high level is depicted below. SOCX-Verifier can be deployed on any testplatform with minimum effort. SOCX-Verifier setup requires providing the necessary driver-models in DPS format and verification intent as scenario specification.


SOCX-Verifier compiles the scenario representation and translates it into a ‘C’ test-application. The test application including the generated device drivers and SOCX-OS are linked together to generate the test software.

SOCX-Verifier generates System-Verilog (SV) classes and a transactional coverage model from scenario specification. These SV classes can be plugged into existing test-bench with minimal effort and provide for unified coverage view and test-bench test-software synchronization.