News & Events

Vayavya Labs focuses on better productivity at a lower cost

Vayavya Labs featured in Economic Times article “Lessons from 50 start-ups”. Find more details here.
By |July 6th, 2012|News|Comments Off on Vayavya Labs focuses on better productivity at a lower cost

Vayavya Labs mentioned in BLOG of ESL coverage at DAC-2012 by Brian Bailey

Vayavya Labs provides leading-edge solutions to accelerate embedded software and firmware development. Its patented device-driver generation technology provides a 10x productivity boost by synthesizing driver code from specs, enabling silicon providers and system vendors to ensure timely delivery of the necessary OS ports and board support packages (BSPs). The programmatic spec capture can be leveraged to define a common pre-silicon to post-silicon validation methodology to streamline verification, lowering R&D cost. Vayavya Labs was recently included on the EE Times Silicon 60. They will demonstrate their Accelerated BSP Development methodology, featuring device-driver synthesis, as well as their System-Level Validation solution. DAC-2012, Booth #710 http://www.eetimes.com/electronics-blogs/other/4373629/Gearing-Up-for-DAC—Above-RTL?Ecosystem=eda-design
By |May 24th, 2012|News|Comments Off on Vayavya Labs mentioned in BLOG of ESL coverage at DAC-2012 by Brian Bailey

Vayavya Labs @ DAC 2012

San Jose, CA, May-12, 2012:   Vayavya Labs, a provider of leading edge solutions that accelerate embedded software and firmware development, announced that it will be presenting its Accelerated BSP Methodology at DAC 2012. The company will also unveil its System-level Validation solution at the show. Both these solutions leverage Vayavya Labs’ patented device driver generation (DDGen) technology.

The DDGen technology provides a 10x productivity boost by synthesizing driver code from specs, thereby enabling silicon providers and system vendors to ensure timely delivery of the necessary OS ports and BSP’s to their customers. The programmatic spec capture can also be leveraged to define a common pre-silicon to post-silicon validation methodology which helps streamline verification, thereby lowering R&D cost.

Vayavya Labs will be presenting these solutions at their booth (#710) at the Moscone Center in San Francisco from Jun 4-6.    For more details on DAC 2012, please CLICK HERE.

By |May 12th, 2012|News|Comments Off on Vayavya Labs @ DAC 2012

ESC session on SD/MMC Command Test Module

One of our key technical architects and linux experts, Pavitra will talk on a  post-silicon validation framework for SD/SDIO/MMC host controllers. This framework enables a user to validate each protocol command individually.. Find more details at: http://www.ubmdesign.com/conference/tracks/ http://www.ubmdesign.com/sessions/esc
By |March 25th, 2012|News|Comments Off on ESC session on SD/MMC Command Test Module

Vayavya Labs appoints Kazuhiro Honjo as consultant Director Sales for Japan.

Japan market has been a leading adopter of emerging technologies and design flows in semiconductor and EDA domain. With increased focus on System-Realization and time-to-market, Vayavya’s embedded software synthesis tools and methodologies are bound to attract the attention of early adopters.

Kazuhiro Honjo-san brings with him an extensive EDA sales and marketing experience in Japan and leads our efforts in reaching the target customers.

By |November 14th, 2011|News|Comments Off on Vayavya Labs appoints Kazuhiro Honjo as consultant Director Sales for Japan.

Model based design methodology and TLMCentral initiative…

Vayavya Joins the TLMCentral initiative by Synopsys, an industry wide web-portal that offers a unique aggregation point for transaction-level models. While the aim of Model Based approach is to speed up software delivery, Vayavya’s tools further this by helping automation of Embedded Software components.

https://vayavyalabs.com//blog/2011/11/08/model-based-design-methodology-and-tlmcentral-initiative http://www.tlmcentral.com/about-tlmcentral/

By |November 7th, 2011|News|Comments Off on Model based design methodology and TLMCentral initiative…

Indian Angel Network invests $1 million in Vayavya Labs.

Indian Angel Network, India’s largest national network of business angels investing in start-ups, has invested $ 1 million in Vayavya Labs. This will provide a major boost for the expansion plans we had for our System Design Automation Tools and strengthens our sales and marketing efforts.

The TIE Bangalore played a major role in bringing about this deal. We appreciate the support and enthusiasm of Mr. Sharad Sharma who said, “Vayavya tools play a pivotal role in adding value by cutting down development, testing and debugging time at customer end thereby meeting the goal for go-to-market.

By |July 24th, 2011|News|Comments Off on Indian Angel Network invests $1 million in Vayavya Labs.

Vayavya Labs is an IIM-B, NSRCEL incubatee company

By |May 24th, 2011|News|Comments Off on Vayavya Labs is an IIM-B, NSRCEL incubatee company

Vayavya Labs to be part of ISA’s business delegation to UK

India Semiconductor Association (ISA), the premier trade body representing the semiconductor industry in the country, is organising a business delegation visit to the UK from 28 September to 2 October 2009. Led by Dr Omkar Rai, senior director, Software Technology Parks of India (STPI), department of information and technology, ministry of communication & IT, Government of India, the delegation includes hardware design and embedded software companies such as Wipro, TCS, Circuitsutra, CMC, KPIT Cummins, Smartplay Technologies, SiWays Microelectronics, United Telecom Ltd and Vayavya Labs. Please click here for more details.

By |December 12th, 2010|News|Comments Off on Vayavya Labs to be part of ISA’s business delegation to UK

Vayavya to present at IP-09 France(Grenoble) a paper on “DDGEN: An Automated Device Driver

By |August 25th, 2010|News|Comments Off on Vayavya to present at IP-09 France(Grenoble) a paper on “DDGEN: An Automated Device Driver