- 30 Jan 2013: Vayavya Labs delivers Linux 3.0 driver for Synopsys Ethernet QoS v4.0 Controller using DDGEN
Vayavya Labs recently delivered a Linux 3.0 device driver for Synopsys Ethernet QoS v4.0. This driver was generated using our flagship device driver synthesis tool DDGEN. The basic driver consisting of single channel DMA and ring mode support will be available as a reference driver along with the IP. Please contact us for a comprehensive driver consisting of the following advanced features:instant payday loans online
- Multi-channel DMA
- VLAN Tag detection Energy Efficient Ethernet
- TCP segmentation offloading
- Audio Video bridging
- Large receive offloading
- Jumbo Frame handling
- Precision Timing Protocol.
- 6 Jul 2012: Vayavya Labs focuses on better productivity at a lower cost
- 24 May 2012: Vayavya Labs mentioned in BLOG of ESL coverage at DAC-2012 by Brian Bailey
Vayavya Labs provides leading-edge solutions to accelerate embedded software and firmware development. Its patented device-driver generation technology provides a 10x productivity boost by synthesizing driver code from specs, enabling silicon providers and system vendors to ensure timely delivery of the necessary OS ports and board support packages (BSPs). The programmatic spec capture can be leveraged to define a common pre-silicon to post-silicon validation methodology to streamline verification, lowering R&D cost. Vayavya Labs was recently included on the EE Times Silicon 60. They will demonstrate their Accelerated BSP Development methodology, featuring device-driver synthesis, as well as their System-Level Validation solution.
- 12 May 2012: Vayavya Labs @ DAC 2012
San Jose, CA, May-12, 2012: Vayavya Labs, a provider of leading edge solutions that accelerate embedded software and firmware development, announced that it will be presenting its Accelerated BSP Methodology at DAC 2012. The company will also unveil its System-level Validation solution at the show. Both these solutions leverage Vayavya Labs’ patented device driver generation (DDGen) technology.
The DDGen technology provides a 10x productivity boost by synthesizing driver code from specs, thereby enabling silicon providers and system vendors to ensure timely delivery of the necessary OS ports and BSP’s to their customers. The programmatic spec capture can also be leveraged to define a common pre-silicon to post-silicon validation methodology which helps streamline verification, thereby lowering R&D cost.
Vayavya Labs will be presenting these solutions at their booth (#710) at the Moscone Center in San Francisco from Jun 4-6. For more details on DAC 2012, please CLICK HERE.
- 25 Mar 2012: ESC session on SD/MMC Command Test Module
One of our key technical architects and linux experts, Pavitra will talk on a post-silicon validation framework for SD/SDIO/MMC host controllers. This framework enables a user to validate each protocol command individually..