Leading chip design verification technology suppliers including us announce the Verification 3.0 Innovation Summit https://globenewswire.com/news-release/2019/02/25/1741777/0/en/Leading-Verification-Technology-Suppliers-Host-Verification-3-0-Innovation-Summit-featuring-Keynote-by-Joe-Costello.html.
We will be presenting the relevance of Hardware Software Interfaces ( HSI), proposed standards for achieving the goals of Portable Stimulus Standards and eventually realizing Software-Driven Verification.
Mark your calendars, register here https://verification30.com
Listen to Karthick, our Principal Architect talk on how an efficient TLM modeling could accelerate virtual platforms and Hybrid based emulations for SoC verification & system-level validation.
With recent DAC at SF as background, EDA veterans discuss the next possible big things: cloud, Software & Portable Stimulus.
Verification 3.0 represents a new plateau in the continuing evolution of semiconductor solutions in general — a new balance in the combination of the various solutions that make up modern verification environments that can be clearly observed.
Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that its Board of Directors has approved Portable Test and Stimulus 1.0 as an Accellera standard. The new standard is available immediately to download for free.