Model based design methodology and TLMCentral initiative…..
8 Nov
Some of you might have seen the press release already (http://synopsys.mediaroom.
For most budding engineers especially one who are being introduced to newer approaches to Software Development ( likes of Model based design methodology) I am giving a little long winded introduction to what this portal is about, starting from fundamentals.
An SoC is built using one or more processors (like ARM, SH4, MIPS etc), a bus network (like AMBA from ARM), few peripherals (interrupt controller, UART, I2C, USB controller, ethernet controller etc) and possibly DSPs/other accelerators. In the process of building a SoC, we perform simulations at various levels. Of particular interest for SW developers is a simulation of SoC that allows us to develop and debug software that will run on the processor. To do this, we need to have register accurate simulation of all peripherals (so device drivers will work correctly) and an instruction accurate simulation of the processor (so cross complied code will work).
Like a lego game where various parts can be assembled together to create complex designs, we usually develop a “model” of the processor and each of the peripherals separately and then put them together to form the system that we wish to develop software on. And like lego blocks, we need a well defined “interface” without which we can’t connect a peripheral to a bus network, or a processor to the bus. Since the peripheral models can come from different companies, it is important that all these companies agree on the same “interface” – otherwise, it is not possible to connect them together.
TLM – transaction level modelling – is that “interface” that various companies have agreed on. As you would expect, this interface was evolved over many years, with many participants contributing on how it should be designed. TLM allows a peripheral to “talk” to a bus, and a bus to “talk” to any peripheral. Further, in software, it is usually very difficult (if not impossible in some cases) to mix implementations in different languages in a single binary. If one peripheral was developed in C, other in java, yet an other in perl – it will be a mess. It was important to agree on a single language – and the language chosen was C++ (due to various reasons). Specifically for modelling hardware, it is important to simulate progress of time, have C++ classes that behave as hardware registers, have C++ classes that behave as signals/wires, etc. “SystemC” is a C++ library that provides such classes. TLM interface is based on SystemC (that is an approximation of truth, but is sufficient for our purposes here).
So, back to TLM Central – it will serve as a repository where any vendor can publish SystemC models implemented on a TLM interface. These can be processor models, bus models or peripherals. Any user can download these, connect them up and have a simulation of an SoC running.
Where does Vayavya Labs come in to picture here? Once the user has integrated all models, he/she needs drivers! Which is what we will be providing, for few of the peripherals.
How else can you contribute? TLM Central can also include blogs on a wide variety of topics. If you have a topic in mind, please write back to me (karthick at the rate vayavyalabs dot com).
